Multi-chip package with a plurality of chip pads arranged in an array

ABSTRACT

A circuit structure of a package carrier including a plurality of chip pads, a first electrode, a second electrode, a third electrode and a fourth electrode is provided. These chip pads are arranged in an M×N array. A first bonding pad, a second bonding pad, a third bonding pad and a fourth bonding pad are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of each of the first, second, third, and fourth bonding pads of the (S−1) th  row rotated by 90 degrees are equal to the orientations of each of the first, second, third and fourth bonding pads of the S th  row, respectively. The first electrode is connected with each first bonding pad. The second electrode is connected with each second bonding pad. The third electrode is connected with each third bonding pad. The fourth electrode is connected with each fourth bonding pad.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 97144960, filed Nov. 20, 2008. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit structure of a packagecarrier and a multi-chip package having the circuit structure, and moreparticularly, to a circuit structure suitable for carrying a pluralityof wire bonding light emitting diode (LED) chips and a multi-chippackage having the circuit structure.

2. Description of Related Art

The advanced countries in the world are all currently devoting time andeffort to the development of opto-electronic material industry. The LEDhas longevity and low power consumption and thus application thereof isbecoming popular. The LED can be used in applications such as largeelectronic billboard, traffic lights, turn signals of vehicles, andillumination. The current LED industry is advancing toward the goal ofhigh brightness and low light loss so that the LED is able to replaceconventional illumination means.

However, to increase the brightness of the LED and to decrease the lightloss thereof, the package method of the LED is a key factor influencingthe brightness, uniformity of illumination, and element lifespan of theLED in addition to improving the structure of the LED itself. In theconventional technology, a plurality of LED chips is packaged on a samesubstrate by means of a multi-chip packaging method to form a multi-chippackage. Therefore, the multi-chip package including a plurality of LEDchips has more diversified brightness and color. The plurality of LEDchips in the multi-chip package may be electrically connected inparallel, in series, or in series-parallel.

In the conventional technology, a plurality of chip pads in themulti-chip package are arranged in arrays and a plurality of bondingpads respectively connected to different electrodes are disposed in aperipheral area of each of the LED chips. The orientations of thebonding pads in the peripheral area of each chip pad are the same. Eachof the LED chips is disposed on each of the chip pads and isrespectively electrically connected to the different bonding pads in theperipheral area of each of the chip pads through a first conductive lineand a second conductive line so that the LED chips are connected to eachother in parallel, in series, or in series-parallel.

When the LED chips in the multi-chip package are electrically connectedin series or in series-parallel, one of the LED chips may berespectively electrically connected to a first bonding pad and a secondbonding pad in the peripheral area of the LED chip through the firstconductive line and the second conductive line. Another LED chip may berespectively electrically connected to the second bonding pad and athird bonding pad in the peripheral area of the LED chip through thefirst conductive line and the second conductive line. Therefore, thewire bonding directions of the mentioned two LED chips are different.

However, in the manufacturing process of wire bonding, changing the wirebonding direction decreases the speed and yield of wire bonding andthereby causes low productivity and high costs. Hence, how to enable LEDchips to be electrically connected in series or in series-parallelwithout changing wire bonding direction is currently an issue to beresolved.

SUMMARY OF THE INVENTION

The present invention provides a circuit structure of a package carrierin which wire bonding direction does not need to be changed in asubsequent wire bonding process.

The present invention further provides a multi-chip package for whichwire bonding direction does not need to be changed in the manufacturingprocess so that the speed and yield of the wire bonding process areincreased.

The present invention provides a circuit structure of a package carriersuitable for carrying a plurality of wire bonding LED chips. The circuitstructure includes a plurality of chips pads, a plurality of firstbonding pads, a plurality of second bonding pads, a plurality of thirdbonding pads, a plurality of fourth bonding pads, a first electrode, asecond electrode, a third electrode, and a fourth electrode. The chippads are arranged in an M×N array for disposing the LED chips. One ofthe first bonding pads, one of the second bonding pads, one of the thirdbonding pads, and one of the fourth bonding pads are sequentiallyarranged in a peripheral area of each chip pad. The orientations of eachof the first to fourth bonding pads in the S^(th) row are different fromthe orientations of each of the first to fourth bonding pads in the(S−1)^(th) row and the (S+1)^(th) row by 90 degrees, the M and N arepositive integers greater than 1 and S is a positive integer in therange of 2˜N. The first electrode has a plurality of first branch linesrespectively connected to the M first bonding pads in the 1^(st)˜N^(th)rows. The second electrode has a plurality of second branch linesrespectively connected to the M second bonding pads in the 1^(st)˜N^(th)rows. The third electrode has a plurality of third branch linesrespectively connected to the M third bonding pads in the 1^(st)˜N^(th)rows. The fourth electrode has a plurality of fourth branch linesrespectively connected to the M fourth bonding pads in the 1^(st)˜N^(th)rows.

In one embodiment of the present invention, the orientations of each ofthe first to fourth bonding pads in the S^(th) row are different fromthe orientations of each of the first to fourth bonding pads in the(S−1)^(th) row with 90 degrees in the counterclockwise direction.

In one embodiment of the present invention, the orientations of each ofthe first to fourth bonding pads in the S^(th) row are different fromthe orientations of each of the first to fourth bonding pads in the(S−1)^(th) row by 90 degrees in the clockwise direction.

In one embodiment of the present invention, the first electrode has afirst main body portion, the second electrode has a second main bodyportion, the third electrode has a third main body portion, the fourthelectrode has a fourth main body portion. The first, second, third, andfourth main body portions are arranged clockwise and in sequence in theperipheral area of the M×N array formed by the chip pads.

In one embodiment of the present invention, the first branch linesextend toward the chip pads from the first main body portions and areconnected respectively with the M first bonding pads of the1^(st)˜N^(th) rows.

In one embodiment of the present invention, the second branch linesextend toward the chip pads from the second main body portions and areconnected respectively with the M second bonding pads of the1^(st)˜N^(th) rows.

In one embodiment of the present invention, the third branch linesextend toward the chip pads from the third main body portions and areconnected respectively with the M third bonding pads of the1^(st)˜N^(th) rows.

In one embodiment of the present invention, the fourth branch linesextend toward the chip pads from the fourth main body portions and areconnected respectively with the M fourth bonding pads of the1^(st)˜N^(th) rows.

In one embodiment of the present invention, the first branch lines andthe second branch lines are alternately arranged.

In one embodiment of the present invention, the third branch lines andthe fourth branch lines are alternately arranged.

The present invention provides a multi-chip package including asubstrate, a plurality of chip pads, a plurality of LED chips, a firstelectrode, a second electrode, a third electrode, and a fourthelectrode. The chip pads are disposed on the substrate and are arrangedin an M×N array. A peripheral area of each of the chip pads includes afirst bonding pad, a second bonding pad, a third bonding pad, and afourth bonding pad arranged clockwise and in sequence. The orientationsof each of the first to fourth bonding pads in the S^(th) rowrespectively are different from the orientations of each of the first tofourth bonding pads in the (S−1)^(th) and the (S+1)^(th) by 90 degrees,wherein M and N are positive integers greater than 1 and S is a positiveinteger in the range of 2˜N. Each of the LED chips is disposed on one ofthe chip pads. The first electrode has a plurality of first branch linesrespectively connected to the M first bonding pads in the 1^(st)˜N^(th)rows. The second electrode has a plurality of second branch linesrespectively connected to the M second bonding pads in the 1^(st)˜N^(th)rows. The third electrode has a plurality of third branch linesrespectively connected to the M third bonding pads in the 1^(st)˜N^(th)rows. The fourth electrode has a plurality of fourth branch linesrespectively connected to the M fourth bonding pads in the 1^(st)˜N^(th)rows. Each LED chip is electrically connected to two of the bonding padson a same side of each LED chip, wherein the two bonding pads areselected from the first, second, third, and fourth bonding pads.

In one embodiment of the present invention, the orientations of each ofthe first to fourth bonding pads in the S^(th) row are different fromthe orientations of each of the first to fourth bonding pads in the(S−1)^(th) by 90 degrees in the counterclockwise direction.

In one embodiment of the present invention, the orientations of each ofthe first to fourth bonding pads in the S^(th) row are different fromthe orientations of each of the first to fourth bonding pads in the(S−1)^(th) row by 90 degrees in the clockwise direction.

In one embodiment of the present invention, the first electrode has afirst main body portion, the second electrode has a second main bodyportion, the third electrode has a third main body portion, the fourthelectrode has a fourth main body portion. The first, second, third, andfourth main body portions are arranged clockwise and in sequence in theperipheral area of the M×N array formed by the chip pads.

In one embodiment of the present invention, the substrate includes aninsulation layer, wherein the first electrode, the second electrode, andthe first to fourth bonding pads are disposed on the insulation layer,and the third electrode and the fourth electrode are disposed under theinsulation layer and pass through the insulation layer to respectivelyconnect to the third and fourth bonding pads.

In one embodiment of the present invention, the multi-chip packagefurther includes a plurality of first conductive lines and a pluralityof second conductive lines, wherein each of the first conductive linesand each of the second conductive lines are respectively electricallyconnected to each LED chip and two of the bonding pads on a same side ofeach LED chip.

In one embodiment of the present invention, the first conductive linesin each pair and the second conductive lines in each pair arerespectively electrically connected to each LED chip and two of thebonding pads on a same side of each LED chip.

In one embodiment of the present invention, the multi-chip packagefurther includes a coating layer disposed on the insulation layer andcovering the first, second, third, and fourth bonding pads. The coatinglayer has a plurality of openings to expose the LED chips and portionsof the first to fourth bonding pads in the peripheral area of each LEDchip, wherein the portions of the first to fourth bonding pads areadjacent to each LED chip.

In one embodiment of the present invention, the coating layer is formedof resin.

In light of the above illustration, the orientations of each of thefirst to fourth bonding pads in the S^(th) row are different from theorientations of each of the first to fourth bonding pads in the(S−1)^(th) row by a quadrant (90 degrees). Therefore, the firstconductive line and the second conductive line may respectively beelectrically connected to two bonding pads on a same side of each LEDchip. As such, in the present invention, the direction of wire bondingdoes not need to be changed when fabricating the first and secondconductive lines.

In order to make the above and other objects, features and advantages ofthe present invention more comprehensible, several embodimentsaccompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A is a schematic view illustrating a circuit structure of apackage carrier according to one embodiment of the present invention.

FIG. 1B is an exploded view illustrating the circuit structure of thepackage carrier of FIG. 1A.

FIG. 2 is a schematic view illustrating a multi-chip package accordingto one embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 1A is a schematic view illustrating a circuit structure of apackage carrier according to one embodiment of the present invention.FIG. 1B is an exploded view illustrating the circuit structure of thepackage carrier of FIG. 1A.

Referring to FIG. 1A and FIG. 1B simultaneously, a circuit structure 100of a package carrier S of the present embodiment is suitable forcarrying a plurality of wire bonding LED chips (not shown). The circuitstructure 100 includes a plurality of chip pads C, a first bonding padP1, a second bonding pad P2, a third bonding pad P3, a fourth bondingpad P4, a first electrode 110, a second electrode 120, a third electrode130, and a fourth electrode 140. The chip pads C are arranged in an M×Narray for disposing the LED chips, the M and N are positive integersgreater than 1. For convenience of illustration, a 3×3 array formed bynine chip pads C is used for the purpose of illustration in the presentembodiment, which, however, is not intended to limit the number of chippads C and the values of M and N of the present invention.

The first bonding pad P1, the second bonding pad P2, the third bondingpad P3, and the fourth bonding pad P4 are sequentially arranged in aperipheral area of each chip pad C. Orientations of each of the first tofourth bonding pads in the S^(th) row are different respectively fromthe first to fourth bonding pads in the (S−1)^(th) and the (S+1)^(th)row by a quadrant (90 degrees), wherein S is a positive integer in therange of 2˜N. In the present embodiment, the orientation of each bondingpad P is, for example, the orientation of each bonding pad P in relationto a center of the chip pad C corresponding to the bonding pad P.

In the present embodiment, when S is 2, the orientations of each of thefirst to fourth bonding pads P1˜P4 in the S^(th) row are differentrespectively from the orientations of each of the first to fourthbonding pads P1˜P4 in the (S−1)^(th) row by a quadrant (90 degrees). Forexample, the orientations of each of the first to fourth bonding padsP1˜P4 in the S^(th) row are different respectively from the orientationsof each of the first to fourth bonding pads P1˜P4 in the (S−1)^(th) rowby 90 degrees in the counterclockwise direction. The orientations ofeach of the first to fourth bonding pads P1˜P4 in the (S+1)^(th) row aredifferent respectively from the orientations of each of the first tofourth bonding pads P1˜P4 in the S row by 90 degrees in thecounterclockwise direction. In other words, the orientations of each ofthe first to fourth bonding pads P1˜P4 in the (S−1)^(th) row rotated by90 degrees in the counterclockwise direction are equal to theorientations of each of the first to fourth bonding pads P1˜P4 in theS^(th) row. The orientations of each of the first to fourth bonding padsP1˜P4 in the S^(th) row rotated by 90 degrees in the counterclockwisedirection are equal to the orientations of each of the first to fourthbonding pads P1˜P4 in the (S+1)^(th) row. Certainly, in otherembodiments, the orientations of each of the first to fourth bondingpads P1˜P4 in the S^(th) row and the (S+1)^(th) row may be differentrespectively from the orientations of each of the first to fourthbonding pads P1˜P4 in the (S−1)^(th) row and the S^(th) row by 90degrees in the clockwise direction.

Referring to FIG. 1A and FIG. 1B again, in order for the M first bondingpads P1 in the 1^(st)˜N^(th) rows to connect to the first electrode 110,the first electrode 110 may have a plurality of first branch lines 112through which the first electrode 110 is respectively connected to the Mfirst bonding pads P1 in the 1^(st)˜N^(th) rows. Similarly, the secondelectrode 120 has a plurality of second branch lines 122 through whichthe second electrode 120 is respectively connected to the M secondbonding pads P2 in the 1^(st)˜N^(th) rows. The third electrode 130 has aplurality of third branch lines 132 through which the third electrode130 is respectively connected to the M third bonding pads P3 in the1^(st)˜N^(th) rows. The fourth electrode 140 has a plurality of fourthbranch lines 142 through which the fourth electrode 140 is respectivelyconnected to the M fourth bonding pads P4 in the 1^(st)˜N^(th) rows.

In addition, in the present embodiment, the first electrode 110 has afirst main body portion 114, the second electrode 120 has a second mainbody portion 124, the third electrode 130 has a third main body portion134, and the fourth electrode 140 has a fourth main body portion 144.Moreover, the first main body portion 114, the second main body portion124, the third main body portion 134, and the fourth main body portion144 are, for example, sequentially arranged in a clockwise direction inthe peripheral area of the M×N array formed by the plurality of chippads C.

In one embodiment of the present invention, the first branch lines 112may extend from the first main body portion 114 to the right and areconnected sequentially to the M first bonding pads P1 of the1^(st)˜N^(th) rows. In one embodiment of the present invention, thesecond branch lines 122 may extend from the second main body portion 124to the left and are connected sequentially to the M second bonding padsP2 of the 1^(st)˜N^(th) rows. From the above illustration, the firstbranch lines 112 and the second branch lines 122 are alternatelyarranged but are not connected.

In one embodiment of the present invention, the third branch lines 132may extend from the third main body portion 134 to the left and areconnected sequentially to the M third bonding pads P3 of the1^(st)˜N^(th) rows. The fourth branch lines 142 may extend from thefourth main body portion 144 to the right and are connected sequentiallyto the M fourth bonding pads P4 of the 1^(st)˜N^(th) rows. From theabove illustration, the third branch lines 132 and the fourth branchlines 142 are alternately arranged but are not connected. It should benoted that the afore-mentioned arrangement of the first to fourth branchlines 112, 122, 132, and 142 is one embodiment of the present inventionand is not intended to limit the scope of the present invention. Personsskilled in the art may make modification and variation thereto withoutdeparting from the scope of the present invention.

A detailed illustration on a multi-chip package having the circuitstructure 100 is given below.

FIG. 2 is a schematic view of a multi-chip package according to oneembodiment of the present invention. Referring to FIG. 1A, FIG. 1B, andFIG. 2, a multi-chip package 200 of the present embodiment includes asubstrate 210, a plurality of chip pads C, a plurality of LED chips 220,a first electrode 110, a second electrode 120, a third electrode 130,and a fourth electrode 140, wherein the chip pads C and the first tofourth electrodes 110, 120, 130, and 140 form the circuit structure 100.

Simultaneously referring to FIG. 1A, FIG. 1B, and FIG. 2, in the presentembodiment, to insulate among the first electrode 110, the secondelectrode 120, the third electrode 130, and the fourth electrode 140,the substrate 210 has an insulation layer 212, and the first electrode110, the second electrode 120, and the first to fourth bonding padsP1˜P4 are all disposed on the insulation layer 212.

The third electrode 130 and the fourth electrode 140 are both disposedunder the insulation layer 212 and pass through the insulation layer 212to respectively connect to the third bonding pad P3 and the fourthbonding pad P4. In FIG. 1A, since the third electrode 130 and the fourthelectrode 140 are both disposed under the insulation layer 212, thethird electrode 130 and the fourth electrode 140 are illustrated withdotted lines. The third electrode 130 and the fourth electrode 140respectively connect to the third bonding pad P3 and the fourth bondingpad P4 via a plurality of through holes (not shown) passing through theinsulation layer 212. Certainly, in other embodiments, the firstelectrode 110, the second electrode 120, the third electrode 130, andthe fourth electrode 140, and the first to fourth bonding pads P1˜P4 mayall be disposed on a same plane via other circuit layouts.

Each of the LED chips 220 is disposed on one of the chip pads C. EachLED chip 220 is electrically connected to two of the bonding pads P on asame side of each LED chip 220, wherein the two bonding pads P areselected from the first bonding pad P1, the second bonding pad P2, thethird bonding pad P3, and the fourth bonding pad P4. For example, themulti-chip package 200 may include a plurality of first conductive lines230 and a plurality of second conductive lines 240, wherein each of thefirst conductive lines 230 and each of the second conductive lines 240are respectively electrically connected to each LED chip 220 and two ofthe bonding pads P on a same side of each LED chip 220. As such, the LEDchips 220 are electrically connected in series-parallel, wherein the LEDchips 220 in a same row are connected in parallel and the LED chips 220in adjacent rows are connected in series.

In the present embodiment, each LED chip 220 has the first conductivelines 230 and the second conductive lines 240 in pairs. It isillustrated in FIG. 2 that the first conductive lines 230 in each pairand the second conductive lines 240 in each pair are respectivelyelectrically connected to each LED chip 220 and two of the bonding padsP on a same side 222 of each LED chip 220. In other words, the firstconductive lines 230 in pair are electrically connected to the LED chip220 and one of the bonding pads P on the side 222 of the LED chip 220and the second conductive lines 240 in pair are electrically connectedto the LED chip 220 and the other of the bonding pads P on the same side222 of the LED chip 220.

It should be noted that in the present embodiment, each of the LED chips220 has four sides 222, 224, 226, and 228. The first conductive lines230 in each pair and the second conductive lines 240 in each pair mayrespectively be electrically connected to two bonding pads P on any sideof each LED chip 220. Each pair of the first conducive lines 230 andeach pair of the second conductive lines 240 are respectivelyelectrically connected to two bonding pads P on a same side of each LEDchip 220.

Compared to the conventional technology, in the present embodiment, theorientations of each of the first to fourth bonding pads P1˜P4 in theS^(th) row of the circuit structure 100 differ respectively with theorientations of each of the first to fourth bonding pads P1˜P4 in the(S−1)^(th) row by 90 degrees. Therefore, the first conductive line 230and the second conductive line 240 may respectively be electricallyconnected to two of the bonding pads P on a same side of each LED chip220. As such, in the present invention, the direction of wire bondingdoes not need to be changed when fabricating the first conductive lines230 and the second conductive lines 240. In light of the above, whenfabricating the multi-chip package 200 of the present embodiment, thespeed and yield of the wire bonding process are improved and thusproductivity is promoted and cost is decreased.

In addition, in the present embodiment, the multi-chip package 200further includes a coating layer 250 disposed on the insulation layer212 and covering the first to fourth electrodes 110, 120, 130, and 140and the first to fourth bonding pads P1˜P4 to protect the first tofourth electrodes 110, 120, 130, and 140 and the first to fourth bondingpads P1˜P4. The coating layer 250 has a plurality of openings OP toexpose the LED chips 220 and portions of the first to fourth bondingpads P1˜P4 in the peripheral area of each LED chip 220, wherein theportions of the first to fourth bonding pads P1˜P4 are adjacent to eachLED chip 220. A material of the coating layer 250 includes insulatingmaterials such as resin.

In summary, the orientations of each of the first to fourth bonding padsin the S^(th) row of the circuit structure of the present invention aredifferent from the orientations of each of the first to fourth bondingpads in the (S−1)^(th) row by 90 degrees. Therefore, the firstconductive line and the second conductive line may respectively beelectrically connected to two bonding pads on a same side of each LEDchip. As such, in the present invention, the direction of wire bondingdoes not need to be changed when fabricating the first or secondconductive lines. In light of the above, when fabricating the multi-chippackage of the present invention, the speed and yield of the wirebonding process are improved and thus productivity is promoted and costis decreased.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A multi-chip package, comprising: a substrate; a plurality of chippads disposed on the substrate, wherein the chip pads are arranged in anM×N array, a peripheral area of each of the chip pads comprises a firstbonding pad, a second bonding pad, a third bonding pad, and a fourthbonding pad arranged in sequence in a clockwise direction, and theorientations of each of the first to fourth bonding pads in the S^(th)row are different respectively from the orientations of each of thefirst to fourth bonding pads in the (S−1)^(th) row and the (S+1)^(th)row by 90 degrees, wherein M and N being positive integers greater than1 and S being a positive integer in the range of 2˜N; a plurality of LEDchips each disposed on one of the chip pads; a first electrodecomprising a plurality of first branch lines respectively connected tothe M first bonding pads in the 1^(st)˜N^(th) rows; a second electrodecomprising a plurality of second branch lines respectively connected tothe M second bonding pads in the 1^(st)˜N^(th) rows; a third electrodecomprising a plurality of third branch lines respectively connected tothe M third bonding pads in the 1^(st)˜N^(th) rows; and a fourthelectrode comprising a plurality of fourth branch lines respectivelyconnected to the M fourth bonding pads in the 1^(st)˜N^(th) rows,wherein each LED chip is electrically connected to two of the bondingpads on a same side of each LED chip, and the two bonding pads areselected from the first, second, third, and fourth bonding pads.
 2. Themulti-chip package according to claim 1, wherein the orientations ofeach of the first to fourth bonding pads in the S^(th) row are differentfrom the orientations of each of the first to fourth bonding pads in the(S−1)^(th) row by 90 degrees in the counterclockwise direction.
 3. Themulti-chip package according to claim 1, wherein the orientations ofeach of the first to fourth bonding pads in the S^(th) row are differentfrom the orientations of each of the first to fourth bonding pads in the(S−1)^(th) row by 90 degrees in the clockwise direction.
 4. Themulti-chip package according to claim 1, wherein the first electrode hasa first main body portion, the second electrode has a second main bodyportion, the third electrode has a third main body portion, the fourthelectrode has a fourth main body portion, and the first, second, third,and fourth main body portions are sequentially arranged clockwise in theperipheral area of the M×N array formed by the chip pads.
 5. Themulti-chip package according to claim 1, wherein the substrate includesan insulation layer, the first electrode, the second electrode, and thefirst to fourth bonding pads are disposed on the insulation layer, andthe third electrode and the fourth electrode are disposed under theinsulation layer and pass through the insulation layer to respectivelyconnect to the third bonding pads and the fourth bonding pads.
 6. Themulti-chip package according to claim 1, further comprising a pluralityof first conductive lines and a plurality of second conductive lines,wherein each of the first conductive lines and each of the secondconductive lines are respectively electrically connected to each LEDchip and two of the bonding pads on a same side of each LED chip.
 7. Themulti-chip package according to claim 6, wherein the first conductivelines in each pair and the second conductive lines in each pair arerespectively electrically connected to each LED chip and two of thebonding pads on a same side of each LED chip.
 8. The multi-chip packageaccording to claim 1, further comprising a coating layer disposed on theinsulation layer and covering the first, second, third, and fourthbonding pads, and the coating layer has a plurality of openings toexpose the LED chips and portions of the first to fourth bonding pads inthe peripheral area of each LED chip, wherein the portions of the firstto fourth bonding pads are adjacent to each LED chip.
 9. The multi-chippackage according to claim 8, wherein the coating layer comprises resin.